US 12,336,213 B2
Multi-gate semiconductor device and method for forming the same
I-Sheng Chen, Taipei (TW); Tzu-Chiang Chen, Hsinchu (TW); Cheng-Hsien Wu, Hsinchu (TW); Ling-Yen Yeh, Hsinchu (TW); and Carlos H. Diaz, Los Altos Hills, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 6, 2023, as Appl. No. 18/164,965.
Application 18/164,965 is a division of application No. 17/011,274, filed on Sep. 3, 2020, granted, now 11,575,046.
Application 17/011,274 is a division of application No. 16/380,135, filed on Apr. 10, 2019, granted, now 10,770,592, issued on Sep. 8, 2020.
Application 16/380,135 is a division of application No. 15/793,521, filed on Oct. 25, 2017, granted, now 10,269,965, issued on Apr. 23, 2019.
Prior Publication US 2023/0187552 A1, Jun. 15, 2023
Int. Cl. H10D 30/62 (2025.01); B82Y 10/00 (2011.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01)
CPC H10D 30/62 (2025.01) [B82Y 10/00 (2013.01); H01L 21/76877 (2013.01); H10D 30/014 (2025.01); H10D 30/023 (2025.01); H10D 30/024 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/021 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H10D 88/00 (2025.01); H10D 88/01 (2025.01); H10D 84/0128 (2025.01); H10D 84/014 (2025.01); H10D 84/0177 (2025.01); H10D 84/0179 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A multi-gate semiconductor device, comprising:
a plurality of nanostructures vertically stacked over a substrate;
a gate dielectric layer including a first portion wrapping around the plurality of nanostructures and a second portion over the plurality of nanostructures;
a gate conductive structure over the gate dielectric layer;
an interfacial layer wrapping around the plurality of nanostructures, wherein the first portion of the gate dielectric layer surrounds the interfacial layer; and
a first insulating spacer alongside the gate conductive structure and over the plurality of nanostructures, wherein a top surface of the gate conductive structure and a top surface of the second portion of the gate dielectric layer are at different levels.