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1. A middle voltage transistor, comprising: a substrate; a gate disposed on the substrate; a gate dielectric layer disposed between the substrate and the gate and a width of the gate dielectric layer is greater than a width of the gate; a composite spacer contacting the gate and disposed at one side of the gate, wherein the composite spacer comprises: a first spacer contacting the gate and disposed at one side of the gate; and a second spacer contacting the first spacer, wherein the first spacer and the second spacer are entirely disposed at a top surface of the gate dielectric layer; a first lightly doping region embedded in the substrate and extending to be under the gate; a second lightly doping region embedded within the first lightly doping region, and the first lightly doping region surrounding the second lightly doping region, wherein the second lightly doping region comprises a first edge, and the first edge is disposed directly under the composite spacer; a source/drain doping region embedded within the second lightly doping region, and the second lightly doping region surrounding the source/drain doping region, wherein the source/drain doping region comprises a second edge; and a silicide layer covering and contacting the source/drain doping region, wherein the silicide layer comprises an end, and the end is disposed between the first edge and the second edge contacting the gate dielectric layer.
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