US 12,336,207 B2
Semi-conductor structure and manufacturing method thereof
Kai Cheng, Jiangsu (CN); and Dandan Zhu, Jiangsu (CN)
Assigned to ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
Appl. No. 17/783,382
Filed by ENKRIS SEMICONDUCTOR, INC., Jiangsu (CN)
PCT Filed Jun. 3, 2020, PCT No. PCT/CN2020/094174
§ 371(c)(1), (2) Date Jun. 8, 2022,
PCT Pub. No. WO2021/243603, PCT Pub. Date Dec. 9, 2021.
Prior Publication US 2023/0015133 A1, Jan. 19, 2023
Int. Cl. H10D 30/01 (2025.01); H01L 21/223 (2006.01); H10D 30/47 (2025.01); H10D 62/10 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01); H10D 62/854 (2025.01)
CPC H10D 30/015 (2025.01) [H01L 21/2233 (2013.01); H10D 30/475 (2025.01); H10D 62/105 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01); H10D 62/854 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semi-conductor structure, comprising:
a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top;
wherein the heterojunction comprises: a source region, a drain region and a gate region between the source region and the drain region,
the P-type ion doped layer in the gate region comprises an activated region and non-activated regions,
P-type doping ions in the activated region are activated,
P-type doping ions in the non-activated regions are passivated,
the non-activated regions comprise at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region, and
the gate insulation layer is located on the non-activated regions to expose the activated region.