US 12,336,206 B2
Heterojunction bipolar transistors with a cut stress liner
Vibhor Jain, Essex Junction, VT (US); Jeffrey Johnson, Essex Junction, VT (US); Viorel Ontalus, Unionville, CT (US); and John J. Pekarik, Underhill, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Nov. 21, 2022, as Appl. No. 17/990,931.
Prior Publication US 2024/0170561 A1, May 23, 2024
Int. Cl. H10D 10/80 (2025.01); H10D 10/01 (2025.01); H10D 62/13 (2025.01)
CPC H10D 10/891 (2025.01) [H10D 10/021 (2025.01); H10D 62/136 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A structure for a heterojunction bipolar transistor, the structure comprising:
an emitter;
a collector including a first section, a second section, and a third section positioned in a first direction between the first section and the second section;
an intrinsic base disposed in a second direction between the emitter and the third section of the collector; and
a stress layer including a first section positioned to overlap with the emitter, the intrinsic base, and the collector, the first section of the stress layer surrounded by a perimeter,
wherein the first section and the second section of the collector are positioned adjacent to the perimeter of the stress layer, the collector has n-type conductivity, and the stress layer contains tensile stress.