| CPC H10D 1/696 (2025.01) [H01G 4/10 (2013.01); H10B 12/03 (2023.02); H10D 1/042 (2025.01); H10D 1/694 (2025.01); H10D 1/716 (2025.01)] | 20 Claims |
|
1. An integrated circuit device comprising:
a lower electrode disposed on a substrate;
an insulating support pattern supporting the lower electrode;
a dielectric film surrounding the lower electrode and the insulating support pattern;
a high-k interface layer, wherein the high-k interface layer is arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, and wherein the high-k interface layer contacts the insulating support pattern and comprises a zirconium oxide layer; and
an upper electrode disposed adjacent to the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.
|
|
9. An integrated circuit device comprising:
a substrate comprising an active region;
a conductive region disposed on the active region;
a capacitor disposed on the conductive region; and
an insulating support pattern supporting a portion of the capacitor,
wherein the capacitor comprises:
a lower electrode comprising a portion contacting the insulating support pattern;
a dielectric film at least partially surrounding the lower electrode and the insulating support pattern;
a high-k interface layer arranged between the lower electrode and the dielectric film and between the insulating support pattern and the dielectric film, and wherein the high-k interface layer contacts the insulating support pattern, and comprises a zirconium oxide layer; and
an upper electrode disposed adjacent to the lower electrode, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and the lower electrode.
|
|
17. An integrated circuit device comprising:
a substrate comprising an active region;
a plurality of conductive regions disposed on the active region;
an insulating pattern disposed on the plurality of conductive regions and extending in a horizontal direction parallel to the substrate, the insulating pattern comprising a plurality of openings that vertically overlap the plurality of conductive regions;
a plurality of lower electrodes penetrating the insulating pattern through the plurality of openings and respectively connected to the plurality of conductive regions, wherein each of the plurality of lower electrodes comprises a first metal;
an insulating support pattern disposed apart from the insulating pattern in a vertical direction and extending in the horizontal direction, the insulating support pattern contacting a portion of each of the plurality of lower electrodes to support the plurality of lower electrodes;
a dielectric film surrounding the plurality of lower electrodes, the insulating pattern, and the insulating support pattern;
a high-k interface layer arranged between the plurality of lower electrodes and the dielectric film, between the insulating support pattern and the dielectric film, and between the insulating pattern and the dielectric film, wherein the high-k interface layer contacts the insulating support pattern, and comprises a zirconium oxide layer; and
an upper electrode disposed adjacent to each of the plurality of lower electrodes, wherein the high-k interface layer and the dielectric film are disposed between the upper electrode and each of the plurality of lower electrodes, and wherein the upper electrode comprises a second metal.
|