US 12,336,199 B2
Semiconductor devices and methods for increased capacitance
Cheng-You Tai, Taipei (TW); Ling-Sung Wang, Tainan (TW); Ru-Shang Hsiao, Jhubei (TW); Jung-Chi Jeng, Tainan (TW); Sung-Hsin Yang, Tainan (TW); and Tsung Jing Wu, Yunlin County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 21, 2022, as Appl. No. 17/699,300.
Prior Publication US 2023/0299213 A1, Sep. 21, 2023
Int. Cl. H01L 21/265 (2006.01); H10D 1/00 (2025.01); H10D 1/66 (2025.01)
CPC H10D 1/66 (2025.01) [H01L 21/26513 (2013.01); H10D 1/047 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising at least one fin, wherein the fin comprises at least a first groove across an entire width of the fin and a second groove across the width of the fin, wherein the first groove and the second groove each include an STI layer, wherein the depths of the STI layers differ from each other;
a first gate stack disposed over the at least one fin, wherein the first gate stack fills the first groove; and
a first source and a first drain, each electrically connected to the at least one fin along a length of the fin;
wherein the first gate stack, the first source, the first drain, and the at least one fin form a transistor.