US 12,336,194 B2
System architecture, structure and method for hybrid random access memory in a system-on-chip
Po-Kai Hsu, Tainan (TW); Hui-Lin Wang, Taipei (TW); Ching-Hua Hsu, Kaohsiung (TW); Yi-Yu Lin, Taichung (TW); Ju-Chun Fan, Tainan (TW); and Hung-Yueh Chen, Hsinchu (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Jan. 23, 2024, as Appl. No. 18/420,684.
Application 18/420,684 is a division of application No. 17/973,557, filed on Oct. 26, 2022, granted, now 11,925,035.
Application 17/973,557 is a division of application No. 17/033,901, filed on Sep. 27, 2020, granted, now 11,522,013, issued on Dec. 6, 2022.
Claims priority of application No. CN202010855208.7 (CN), filed on Aug. 24, 2020.
Prior Publication US 2024/0172456 A1, May 23, 2024
Int. Cl. H10B 63/00 (2023.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/80 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02); H10N 70/063 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/8833 (2023.02)] 1 Claim
OG exemplary drawing
 
1. A method of manufacturing a hybrid random access memory in a system-on-chip, the method comprising:
providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region, a resistive random-access memory (ReRAM) region and an interlayer dielectrics (ILD) formed on said semiconductor substrate;
forming multiple ReRAM cells in said ReRAM region on said semiconductor substrate, wherein steps of forming said ReRAM cells comprises:
forming a bottom electrode in a first dielectric capping layer on said interlayer dielectrics, wherein said first dielectric capping layer physically touches said interlayer dielectrics, so that top surfaces of said bottom electrode and said first dielectric capping layer are flush and said bottom electrode physically touches a contact formed in said interlayer dielectrics, and said contact is directly connected to an active area of underlying said semiconductor substrate;
forming a variable resistive layer and a first top electrode layer sequentially on said bottom electrode;
performing a first photolithography process to pattern said first top electrode layer and said variable resistive layer;
covering a spacer layer on said first top electrode layer and said variable resistive layer; and
performing an etching process to said spacer layer to form spacers on sidewalls of said variable resistive layer and said first top electrode layer;
forming a first dielectric layer on said first dielectric capping layer, wherein said ReRAM cells are in said first dielectric layer and said first dielectric layer is a first inter-metal layer (IMD1);
forming a first metal layer (M1) in said first dielectric layer;
forming a second dielectric capping layer on said first dielectric layer, said second dielectric capping layer directly contacting said patterned first top electrode layer;
forming multiple MRAM cells in said MRAM region on said first dielectric layer, wherein steps of forming said MRAM cells comprises:
forming a bottom electrode layer, a magnetic tunnel junction component and a second top electrode layer in order, wherein said bottom electrode layer is connected directly to a via below, and said via is further connected to an underlying metal layer;
performing a second photolithography process to pattern said bottom electrode layer, said magnetic tunnel junction component and said second top electrode layer; and
forming a capping layer to cover said MRAM cells;
forming a second dielectric layer on said first dielectric layer, wherein said MRAM cells are in said second dielectric layer.