US 12,336,191 B2
Magnetic memory including transistors and magnetoresistive elements respectively connected between a conductive plate and a conductive line and additional transistors each connected between the conductive line and another conductive line
Yoshihiro Ueda, Yokohama Kanagawa (JP); and Masatoshi Yoshikawa, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Feb. 28, 2023, as Appl. No. 18/176,464.
Claims priority of application No. 2022-124374 (JP), filed on Aug. 3, 2022.
Prior Publication US 2024/0049475 A1, Feb. 8, 2024
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/22 (2023.02) [G11C 11/161 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 11/1697 (2013.01); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A magnetic memory comprising:
a plurality of first conductive lines extending in a first direction;
a second conductive line extending in a second direction intersecting the first direction;
a third conductive line;
a fourth conductive line;
a first conductive plate that is electrically isolated from the third conductive line and the fourth conductive line;
a plurality of magnetoresistive elements, each of which is arranged between the first conductive plate and the second conductive line and includes a first magnetic layer, a second magnetic layer between the first magnetic layer and the second conductive line, and a first non-magnetic layer between the first magnetic layer and the second magnetic layer;
a plurality of first transistors, each of which is connected between the first conductive plate and a corresponding one of the magnetoresistive elements, and has a gate which is a part of one of the first conductive lines;
a second transistor that is connected between a first end of the second conductive line and the third conductive line;
a third transistor that is connected between a second end of the second conductive line and the fourth conductive line; and
a controller configured to control voltages applied to the first conductive lines, and the third and fourth conductive lines during a read operation or a write operation.