| CPC H10B 61/22 (2023.02) [G11C 11/161 (2013.01); G11C 11/1673 (2013.01); H10N 50/01 (2023.02); H10N 50/80 (2023.02); G11C 11/1675 (2013.01)] | 10 Claims |

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1. A magnetic array comprising:
a substrate;
a first unit;
a second unit;
a word line;
a first read line;
a second read line;
a first gate line;
a second gate line; and
a source line,
wherein each of the first unit and the second unit includes a magnetoresistance effect element, a first switching element, and a second switching element,
wherein the magnetoresistance effect element includes a laminate and a wiring provided on the laminate,
wherein the laminate includes at least a reference layer and a non-magnetic layer in order from a substrate side,
wherein the first switching element of the first unit is connected to the reference layer of the first unit and the first switching element of the second unit is connected to the reference layer of the second unit,
wherein the second switching element of the first unit is connected to the wiring of the first unit, and the second switching element of the second unit is connected to the wiring of the second unit,
wherein the first read line is connected to the first switching element of the first unit, the first read line being configured to conduct a read current when data is read from the magnetoresistance effect element,
wherein the second read line is connected to the first switching element of the second unit, the second read line being configured to conduct the read current when data is read from the magnetoresistance effect element,
wherein the word line is connected to the second switching elements of the first unit and the second unit, the word line being configured to conduct a write current when data is written to the magnetoresistance effect element,
wherein the first gate line is connected to a gate of the first switching element of the first unit and a gate of the second switching element of the second unit, the first gate line being configured to control ON/OFF operation of the first switching element and the second switching element,
wherein the second gate line is connected to a gate of the second switching element of the first unit and a gate of the first switching element of the second unit, the second gate line being configured to control ON/OFF operation of the first switching element and the second switching element, and
wherein the source line is connected to the wiring of the first unit and the wiring of the second unit, the source line being configured to conduct the read current and the write current.
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