US 12,336,187 B2
Mobility enhancement by source and drain stress layer or implantation in thin film transistors
Hui-Hsien Wei, Taoyuan (TW); Yen-Chung Ho, Hsinchu (TW); Chia-Jung Yu, Hsinchu (TW); Yong-Jie Wu, Hsinchu (TW); and Pin-Cheng Hsu, Zhubei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Aug. 9, 2023, as Appl. No. 18/446,755.
Application 18/446,755 is a division of application No. 17/368,869, filed on Jul. 7, 2021, granted, now 11,825,661.
Claims priority of provisional application 63/082,110, filed on Sep. 23, 2020.
Prior Publication US 2023/0389333 A1, Nov. 30, 2023
Int. Cl. H10D 30/69 (2025.01); H10B 53/30 (2023.01); H10D 30/67 (2025.01)
CPC H10B 53/30 (2023.02) [H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/794 (2025.01); H10D 30/791 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a planar insulating spacer layer located over a substrate;
a combination of a semiconducting material layer, a thin film transistor (TFT) gate dielectric layer, and a gate electrode located over the planar insulating spacer layer;
a dielectric matrix layer located over the combination of the semiconducting material layer, the TFT gate dielectric layer, and the gate electrode, wherein an entirety of a top surface of the dielectric matrix layer is substantially planar and is located within a horizontal plane;
a source-side via cavity and a drain-side via cavity that vertically extend through the dielectric matrix layer and into upper end portions of the semiconducting material layer;
a source structure filling an entire volume of the source-side via cavity and consisting of a source-side metallic liner and a source-side metallic fill material portion; and
a drain structure filling an entire volume of the drain-side via cavity and consisting of a drain-side metallic liner and a drain-side metallic fill material portion,
wherein the source-side metallic liner and the drain-side metallic liner generate tensile stress or compressive stress on the end portions of the semiconducting material layer;
wherein a lattice constant of the end portions of the semiconducting material layer differs from a lattice constant of a center portion of the semiconducting material layer such that the center portion of the semiconducting material layer is under a mechanical stress between the end portions of the semiconducting material layer;
wherein an entirety of the semiconductor material layer has a uniform material composition throughout;
wherein an entirety of a top surface of the source-side metallic liner and an entirety of a top surface of the source-side metallic fill material portion are located within the horizontal plane;
wherein an entirety of a top surface of the drain-side metallic liner and an entirety of a top surface of the drain-side metallic fill material portion are located within the horizontal plane; and
wherein each of the source-side metallic liner and the drain-side metallic liner comprises a respective sidewall segment in direct contact with a respective sidewall surface segment the semiconducting material layer and further comprises a respective bottom surface in direct contact with a respective recessed surface segment of the semiconducting material layer.