US 12,336,184 B1
Methods of fabricating trench capacitors on a shared plate electrode
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Rafael Rios, Austin, TX (US); Amrita Mathuriya, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Mauricio Manfrini, Heverlee (BE); Rajeev Kumar Dokania, Beaverton, OR (US); Somilkumar J. Rathi, San Jose, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Mar. 18, 2022, as Appl. No. 17/655,420.
Application 17/655,420 is a continuation of application No. 17/654,917, filed on Mar. 15, 2022.
Int. Cl. H10B 53/30 (2023.01); H10B 69/00 (2023.01)
CPC H10B 53/30 (2023.02) [H10B 69/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a device structure, the method comprising:
forming at least a first conductive interconnect in a first dielectric in a memory region and a second conductive interconnect in a first dielectric in a logic region;
depositing an etch stop layer on the first dielectric and on the first conductive interconnect and on the second conductive interconnect;
forming an electrode structure on the first conductive interconnect by etching a first opening in the etch stop layer and depositing a first conductive hydrogen barrier layer and a first conductive material in the first opening;
depositing a conductive layer on the electrode structure and on the etch stop layer;
forming a mask on the conductive layer;
etching the conductive layer to form a plate electrode;
depositing a second dielectric on the plate electrode and on the etch stop layer;
forming a plurality of trench capacitors on the plate electrode by a process, comprising:
forming a plurality of trenches in the second dielectric, wherein individual ones of the plurality of trenches expose the plate electrode;
forming a dielectric spacer on sidewalls of the individual ones of the plurality of trenches;
depositing a first electrode layer on a base and adjacent to the dielectric spacer, wherein the first electrode layer comprises a first conductive nonlinear polar material;
depositing a dielectric layer comprising a perovskite material on the first electrode layer; and
depositing a second electrode layer on the dielectric layer, wherein the second electrode layer comprises a second conductive nonlinear polar material;
forming a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are formed on an individual ones of the plurality of trench capacitors;
forming a second opening in the second dielectric and in the etch stop layer, wherein the second opening is formed above the second conductive interconnect;
depositing a conductive material in the second opening to form a via structure on the second conductive interconnect; and
forming a metal structure on the via structure.