US 12,336,180 B2
Memory cell array with increased source bias voltage
Chen-Jun Wu, Hsinchu (TW); Sun Yi Chang, New Taipei (TW); Sheng-Chih Lai, Hsinchu (TW); and Chung-Te Lin, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/818,343.
Prior Publication US 2024/0049470 A1, Feb. 8, 2024
Int. Cl. G11C 16/04 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01); G11C 13/00 (2006.01); G11C 16/08 (2006.01); H10B 41/30 (2023.01); H10B 43/30 (2023.01); H10B 51/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H10B 43/30 (2023.02) [G11C 11/1657 (2013.01); G11C 11/2257 (2013.01); G11C 13/0028 (2013.01); G11C 16/08 (2013.01); H10B 41/30 (2023.02); H10B 51/30 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory cell array comprising:
a plurality of memory cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of memory cells comprises a dual-gate transistor, the dual-gate transistor comprising a silicon substrate, a channel layer over the silicon substrate, a first gate structure under the channel layer, and a second gate structure over the channel layer;
a plurality of word lines extending in a first direction and electrically connected to the plurality of rows, respectively, and wherein the first gate structure and the second gate structure of the dual-gate transistor of each of the plurality of memory cells are electrically connected to and share one of the plurality of word lines, the first gate structure and the second gate structure being equally biased;
a plurality of source lines extending in a second direction and electrically connected to the plurality of columns, respectively; and
a plurality of bit lines extending in the second direction and electrically connected to the plurality of columns, respectively; and
wherein a plurality of inactivated word lines are configured to be applied a bias voltage that is zero, and the plurality of source lines are configured to be applied a positive bias voltage.