US 12,336,178 B2
Nonvolatile memory device
Kyunghwa Yun, Hwaseong-si (KR); Chanho Kim, Seoul (KR); and Dongku Kang, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 8, 2022, as Appl. No. 17/860,618.
Application 17/860,618 is a continuation of application No. 16/878,756, filed on May 20, 2020, granted, now 11,430,806.
Claims priority of application No. 10-2019-0128221 (KR), filed on Oct. 16, 2019.
Prior Publication US 2022/0352204 A1, Nov. 3, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a peripheral circuit that includes a first active region and a plurality of elements formed on the first active region; and
a memory block comprising:
a second active region on the peripheral circuit;
a vertical structure including a plurality of layer pairs, each layer pair including an insulating layer and a conductive layer that extend along a first direction and that are stacked on the second active region in a stacking direction perpendicular to the first direction;
a first insulating layer on the vertical structure;
a first partial conductive layer and a second partial conductive layer on the first insulating layer, the first partial conductive layer and the second partial conductive layer being spaced apart from each other along the first direction to expose a region of the first insulating layer;
a second partial insulating layer on the first partial conductive layer;
a third partial insulating layer on the second partial conductive layer;
a third partial conductive layer on the second partial insulating layer;
a fourth partial conductive layer on the third partial insulating layer;
a plurality of first vertical channels that penetrate the third partial conductive layer, the second partial insulating layer, the first partial conductive layer, the first insulating layer, and the vertical structure in the stacking direction; and
a plurality of second vertical channels that penetrate the fourth partial conductive layer, the third partial insulating layer, the second partial conductive layer, the first insulating layer, and the vertical structure in the stacking direction,
wherein the first partial conductive layer and the second partial conductive layer are electrically connected to a first through via that penetrates the second active region, the vertical structure and the region of the first insulating layer that is exposed between the first partial conductive layer and the second partial conductive layer, between the second partial insulating layer and the third partial insulating layer, and between the third partial conductive layer and the fourth partial conductive layer, and
wherein the third partial conductive layer and the fourth partial conductive layer are electrically connected to a second through via that penetrates the second active region, the vertical structure and the region of the first insulating layer that is exposed between the first partial conductive layer and the second partial conductive layer, between the second partial insulating layer and the third partial insulating layer, and between the third partial conductive layer and the fourth partial conductive layer.