US 12,336,177 B2
Nonvolatile memory device and method for fabricating the same
Soodoo Chae, Seongnam-si (KR); Myoungbum Lee, Seoul (KR); HuiChang Moon, Yongin-si (KR); Hansoo Kim, Suwon-si (KR); JinGyun Kim, Yongin-si (KR); Kihyun Kim, Hwaseong-si (KR); Siyoung Choi, Seongnam-si (KR); and Hoosung Cho, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 8, 2021, as Appl. No. 17/497,417.
Application 17/497,417 is a continuation of application No. 16/708,482, filed on Dec. 10, 2019, granted, now 11,387,249.
Application 16/708,482 is a continuation of application No. 15/634,597, filed on Jun. 27, 2017, granted, now 10,546,872, issued on Jan. 28, 2020.
Application 15/634,597 is a continuation of application No. 14/973,182, filed on Dec. 17, 2015, granted, now 9,735,170, issued on Aug. 15, 2017.
Application 14/973,182 is a continuation of application No. 14/027,599, filed on Sep. 16, 2013, granted, now 9,245,839, issued on Jan. 26, 2016.
Application 14/027,599 is a continuation of application No. 12/592,869, filed on Dec. 3, 2009, granted, now 8,541,831, issued on Sep. 24, 2013.
Claims priority of application No. 10-2008-0121886 (KR), filed on Dec. 3, 2008; and application No. 10-2009-0016406 (KR), filed on Feb. 26, 2009.
Prior Publication US 2022/0037355 A1, Feb. 3, 2022
Int. Cl. H10B 43/27 (2023.01); H01L 23/498 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/50 (2023.01); H10D 30/69 (2025.01); H10D 64/00 (2025.01)
CPC H10B 43/27 (2023.02) [H01L 23/49844 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/50 (2023.02); H10D 30/694 (2025.01); H10D 64/118 (2025.01); H01L 2924/0002 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A three-dimensional semiconductor device comprising:
a first alternating stack of first dielectric layers and first electrically conductive layers on a substrate;
a second alternating stack of at least one second dielectric layer and at least one second electrically conductive layer on the first alternating stack;
a memory cell region including a plurality of channel hole structures that vertically extend through each layer of the first alternating stack and the second alternating stack;
a contact region including first stepped surfaces of the first alternating stack and a second stepped surface of the second alternating stack; and
a plurality of dielectric supporter structures including a dielectric material, and extending through the first alternating stack,
wherein the plurality of dielectric supporter structures are laterally spaced apart from the at least one second dielectric layer and the at least one second electrically conductive layer.
 
10. A three-dimensional semiconductor device comprising:
a first alternating stack of first dielectric layers and first electrically conductive layers on a substrate;
a second alternating stack of at least one second dielectric layer and at least one second electrically conductive layer on the first alternating stack;
a memory cell region including a plurality of channel hole structures that vertically extend through each layer of the first alternating stack and the second alternating stack;
a contact region including first stepped surfaces of the first alternating stack and a second stepped surface of the second alternating stack;
a plurality of dielectric supporter structures including a dielectric material, and extending through the first alternating stack; and
a dielectric region on the first stepped surfaces,
wherein the dielectric region continuously extends from a surface of a bottommost first dielectric layer of the first alternating stack to a level of a surface of a topmost second dielectric layer of the second alternating stack,
wherein the dielectric region is on sidewalls of the plurality of dielectric supporter structures, and
wherein the plurality of dielectric supporter structures are laterally spaced apart from the at least one second dielectric layer and the at least one second electrically conductive layer.