| CPC H10B 41/30 (2023.02) [H10B 41/10 (2023.02)] | 18 Claims |

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1. A memory device, comprising:
a plurality of stack structures arranged along a first direction on an array area of a substrate, wherein each of the stack structures extends along a second direction different from the first direction, in a cross-sectional view of the memory device, each of the stack structures comprises, in sequence from the substrate, a charge storage structure, a control gate, and a cap layer, and the cap layer has a multilayer structure;
a protective layer covering sidewalls of the stack structures,
wherein a width in the first direction of the charge storage structure, a width in the first direction of the control gate, and a width in the first direction of the cap layer are substantially equal to each other, and
a plurality of contact plugs respectively disposed on the substrate among the plurality of stack structures, wherein heights of the contact plugs relative to the substrate and heights of the stack structures relative to the substrate are substantially the same.
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