US 12,336,174 B2
Memory structure having air gap and method for manufacturing the same
Meng-Han Lin, Hsinchu (TW); and Chia-En Huang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 29, 2022, as Appl. No. 17/707,562.
Prior Publication US 2023/0320084 A1, Oct. 5, 2023
Int. Cl. H10B 41/27 (2023.01); H01L 23/48 (2006.01); H10B 41/10 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10D 62/10 (2025.01)
CPC H10B 41/27 (2023.02) [H01L 23/481 (2013.01); H10B 41/10 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10D 62/115 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate; and
a memory structure disposed over the substrate and including:
a pair of first conductive lines,
a channel element disposed between the pair of first conductive lines,
an air gap located in the channel element,
a first memory element disposed to separate one of the pair of first conductive lines from the channel element, and
a second memory element disposed to separate the other one of the pair of first conductive lines from the channel element,
wherein the memory structure further includes a pair of second conductive lines disposed transversely relative to the pair of first conductive lines and at two opposite sides of the channel element such that each of the second conductive lines is in contact with the channel element and the first memory element and the second memory element.