US 12,336,173 B2
Anti-fuse one-time programmable nonvolatile memory cell and memory thereof
Ming Wang, Sichuan (CN); Teng Feng Wang, Sichuan (CN); and Meifang Lee, Sichuan (CN)
Assigned to CHENGDU ANALOG CIRCUIT TECHNOLOGY INC
Filed by Chengdu Analog Circuit Technology Inc, Sichuan (CN)
Filed on Sep. 7, 2021, as Appl. No. 17/467,774.
Claims priority of application No. 202110759548.4 (CN), filed on Jul. 6, 2021.
Prior Publication US 2023/0011223 A1, Jan. 12, 2023
Int. Cl. H10B 20/25 (2023.01)
CPC H10B 20/25 (2023.02) 6 Claims
OG exemplary drawing
 
1. A one-time programmable nonvolatile memory cell, comprising:
a substrate, providing a first conductivity type well and a second conductivity type well that are adjacent; the first conductivity type well having a first active region, and the second conductivity type well having a second active region, the first active region and the second active region that are adjacent being separated by an isolation region which spans the first and the second conductivity type wells; and the first and second active regions and the isolation region being arranged parallel to each other along a first direction;
a first MOS transistor, located on the first active region and comprising a floating gate and a floating gate oxide below the floating gate; and
a second MOS transistor, comprising an auxiliary gate, an auxiliary gate oxide below the auxiliary gate, a source, and a drain, wherein the second active region comprises two conductive ion-doped regions respectively located at both sides of the auxiliary gate to form the source and the drain; the auxiliary gate is connected with the floating gate, one end of the floating gate and one end of the floating gate oxide of the first MOS transistor are extended from an edge of the first active region, along a second direction perpendicular to the first direction, to form the auxiliary gate and the auxiliary gate oxide respectively, and the auxiliary gate and the auxiliary gate oxide pass through the isolation region until to cover an entire of the second active region; wherein a ratio of an area of the floating gate on the first active region to an area of the auxiliary gate on the second active region is 5:1-35:1;
wherein the first conductivity type well is an N well, and the first active region comprises two P-type doped regions respectively located at both sides of the floating gate along the first direction to serve as a source and a drain of the first MOS transistor, respectively, which is a PMOS transistor; and the second conductivity type well is a P well, and the second active region comprises two N-type doped regions respectively located at both sides of the auxiliary gate along the first direction to form the second MOS transistor which is an NMOS transistor.