US 12,336,170 B2
Semiconductor structure having two word lines covering part of opposite side surfaces of the plurality of semiconductor channels
Guangsu Shao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 25, 2022, as Appl. No. 17/952,265.
Claims priority of application No. 202210556171.7 (CN), filed on May 20, 2022.
Prior Publication US 2023/0017055 A1, Jan. 19, 2023
Int. Cl. H10B 12/00 (2023.01); G11C 5/06 (2006.01)
CPC H10B 12/482 (2023.02) [G11C 5/063 (2013.01); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a plurality of semiconductor channels positioned on the substrate, and the plurality of semiconductor channels being arranged in an array along a first direction and a second direction;
bit lines extending along the first direction, the bit lines being positioned in the substrate, and each of the bit lines being electrically connected to the plurality of semiconductor channels arranged along the first direction;
word lines extending along the second direction, the word lines wrapping part of side surfaces of the plurality of semiconductor channels arranged along the second direction, one of the word lines comprising two sub word lines arranged at intervals along the first direction, and the sub word lines covering part of opposite side surfaces of the plurality of semiconductor channels along the first direction; and
isolation structures, the isolation structures being positioned between adjacent two of the word lines and between adjacent two of the sub word lines respectively.