US 12,336,161 B2
Semiconductor structure and manufacturing method thereof
Chih-Cheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Anhui (CN)
Filed on Jun. 2, 2022, as Appl. No. 17/830,618.
Application 17/830,618 is a continuation of application No. PCT/CN2022/070324, filed on Jan. 5, 2022.
Claims priority of application No. 202111094836.9 (CN), filed on Sep. 17, 2021.
Prior Publication US 2023/0091786 A1, Mar. 23, 2023
Int. Cl. H01L 27/11 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H10B 10/00 (2023.01)
CPC H10B 10/18 (2023.02) [H01L 21/32139 (2013.01); H01L 23/5223 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a gate structure on the substrate, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer; and
an interconnect structure comprising a first interconnect sub-structure and a second interconnect sub-structure, wherein the second interconnect sub-structure protrudes from the first interconnect sub-structure,
wherein the first interconnect sub-structure is connected with the substrate and in direct contact with a side surface of the gate electrode layer, and the second interconnect sub-structure is connected with a top of the gate structure and in direct contact with a top surface of the gate electrode layer.