| CPC H04W 74/0808 (2013.01) [H04L 47/129 (2022.05); H04W 84/12 (2013.01)] | 20 Claims |

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1. An apparatus comprising:
at least one processor; and
at least one memory storing instructions that, when executed with the at least one processor, cause the apparatus at least to:
decode at least a first part of a first frame received on a first channel;
detect, during said decoding the first part of the first frame, transmission of a second frame on a second channel;
in response to said detecting, buffer at least a first part of the second frame, the first part of the second frame comprising duration information;
after said decoding the first part of the first frame, decode at least the first part of the second frame;
update, on the basis of the duration information, channel occupation information of the second channel;
start, based at least partly on the channel occupation information of the second channel indicating that the second channel not occupied, contention for channel access on the second channel.
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