CPC H04W 72/23 (2023.01) [H04W 72/30 (2023.01); H04W 56/001 (2013.01)] | 20 Claims |
1. An apparatus for wireless communication at a user equipment (UE), comprising:
one or more processors; and
one or more memories coupled with the one or more processors and storing processor-executable code that, when executed by the one or more processors, is configured to cause the apparatus to:
receive a synchronized signal block (SSB) including a physical broadcast channel (PBCH);
receive a group of control resource sets (CORESETS) in accordance with receiving the PBCH, each CORESET of the group of CORESETS being a type 0 CORESET (CORESET0) associated with a Type0 physical downlink control channel (Type0-PDCCH), each CORESET of the group of CORESETS being quasi co-located with the SSB, such that the Type0-PDCCH uses a same beam as the SSB; and
receive one or more physical downlink control channels (PDSCHs) in accordance with receiving the group of CORESETS.
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