US 12,335,498 B2
Encoder, decoder, encoding method, and decoding method
Virginie Drugeon, Darmstadt (DE); Tadamasa Toma, Osaka (JP); Takahiro Nishi, Nara (JP); Kiyofumi Abe, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Feb. 7, 2024, as Appl. No. 18/435,124.
Application 18/435,124 is a continuation of application No. 17/547,608, filed on Dec. 10, 2021, granted, now 11,936,886.
Application 17/547,608 is a continuation of application No. PCT/JP2020/023903, filed on Jun. 18, 2020.
Claims priority of provisional application 62/862,892, filed on Jun. 18, 2019.
Prior Publication US 2024/0214589 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/196 (2014.01); H04N 19/31 (2014.01); H04N 19/46 (2014.01); H04N 19/70 (2014.01)
CPC H04N 19/196 (2014.11) [H04N 19/31 (2014.11); H04N 19/46 (2014.11); H04N 19/70 (2014.11)] 5 Claims
OG exemplary drawing
 
1. An encoder comprising:
memory; and
circuitry coupled to the memory and configured to:
store one or more first parameters for each of temporal sub-layers in buffering period supplemental enhancement information (SEI), the one or more first parameters indicating initial delays in timing for extracting data from a coded picture buffer (CPB); and
store a second parameter in the buffering period SEI, the second parameter indicating a number of the one or more first parameters, wherein
a third parameter is included in a Hypothetical Reference Decoder (HRD) parameter syntax, and
the third parameter indicates a number of schedules and has a value equal to a value of the second parameter.