| CPC H04L 9/0631 (2013.01) | 10 Claims |
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1. A storage controller system, comprising:
a memory;
a processor coupled to the memory;
a plurality of data processing units; and
the processor communicates with the plurality of data processing units to cause each of the plurality of data processing units to independently perform an end-to-end encryption operation associated with Advanced Encryption Standard (AES) on a data block;
there is a selected key length, from a plurality of supported key lengths associated with the AES;
the number of data processing units in the plurality of data processing units is selected based at least in part on a desired processing throughput rate and power consumption, wherein the number of data processing units in the plurality of data processing units and the selected key length produce a total processing throughput rate, collectively for the plurality of data processing units, that is a multiple of one or more of the following: 1/10, 1/12 or 1/14 of a maximum throughput rate;
the processor communicates with a scheduler to cause the scheduler to select a target data processing unit, from the plurality of data processing units, including by:
sequentially communicating with the plurality of data processing units in a round-robin order to obtain an idle state information until an idle data processing unit in the plurality of data processing units is encountered; and
selecting the idle data processing unit to be the target data processing unit; and
the processor communicates with the target data processing unit to cause the target data processing unit to:
receive a target data block that is to be encrypted; and
generate a ciphertext data block corresponding to the target data block, including by performing the end-to-end encryption operation associated with AES, including all SubByte transformations, all ShiftRow transformations, all MixColumn transformations, and all AddRoundKey transformations on the target data block.
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