| CPC H04L 5/0048 (2013.01) [H04W 4/70 (2018.02); H04W 72/23 (2023.01); H04W 72/044 (2013.01)] | 21 Claims |

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1. An apparatus, comprising
a memory; and
a processor coupled to the memory, the processor configured to cause the apparatus to:
receive a set of reference signals; and
receive a downlink control channel based at least in part on the received set of reference signals,
wherein an antenna port associated with a reference signal of the received set of reference signals is associated with a precoder of a set of precoders,
wherein the antenna port and the precoder are based at least in part on a time duration and a frequency band; and
wherein the precoder is based at least in part on the antenna port, the time duration, or the frequency band, or a combination thereof.
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