US 12,335,170 B2
Virtual physical circuit for on-chip communication
Kar Leong Wong, Folsom, CA (US); and Satheesh Chellappan, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2022, as Appl. No. 17/704,666.
Prior Publication US 2022/0217099 A1, Jul. 7, 2022
Int. Cl. H04L 49/109 (2022.01)
CPC H04L 49/109 (2013.01) 18 Claims
OG exemplary drawing
 
1. A communication system comprising:
a first virtual physical (vPhy) circuit couplable to a host through a first vPhy interface;
a second vPhy circuit couplable to a device through a second vPhy interface; and
a vPhy-to-vPhy interface to couple to the first vPhy circuit and to the second vPhy circuit, the vPhy-to-vPhy interface including a first data toggle signal line to transmit a first data toggle signal directed from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal line to transmit a second data toggle signal directed from the second vPhy circuit to the first vPhy circuit,
wherein the first vPhy circuit is to generate the first data toggle signal based on a first signal received from the host for transmission to the device, and the second vPhy circuit is to generate the second data toggle signal based on a second signal received from the device for transmission to the host, wherein the first vPhy circuit is to generate a non-return-to-zero inverted (NRZI) input signal to be provided as an input to the host through the first vPhy interface based on the second data toggle signal.