| CPC H04L 43/18 (2013.01) [H04L 43/106 (2013.01); H04L 47/32 (2013.01); H04L 47/34 (2013.01); H04L 69/163 (2013.01)] | 28 Claims |

|
1. A system comprising:
a processor and a memory coupled therewith, the memory storing computer-executable instructions that when executed by the processor, causes the processor to:
receive a plurality of packets of an electronic data message from a source via a network for processing by the processor, each packet of the plurality of packets including either event dependent or event independent data and further characterized by data indicative of a sequence of that packet relative to others of the plurality of packets of the electronic data message;
augment each received packet with a timestamp upon receipt indicative of a time thereof; and
determine, without regard as to whether any of the plurality of packets includes event dependent or event independent data, that at least one of the received augmented packets was received in an order different from the sequence between the plurality of packets by comparing the data indicative of the sequence with the corresponding timestamp of each received augmented packet to determine if the order of receipt of the received augmented packets corresponds to the sequence between the received augmented packets, and
based on the determination, delay processing of the electronic data message.
|