US 12,335,074 B2
Multi-tap decision feed-forward equalizer with precursor and postcursor taps
Chaitanya Palusa, San Jose, CA (US); Rob Abbott, Ontario (CA); Wei-Li Chen, Hsinchu (TW); Po-Hsiang Lan, Taipei (TW); Dirk Pfaff, Ontario (CA); and Cheng-Hsiang Hsieh, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 12, 2024, as Appl. No. 18/602,492.
Application 18/602,492 is a continuation of application No. 17/814,641, filed on Jul. 25, 2022, granted, now 11,962,441.
Application 17/814,641 is a continuation of application No. 17/164,325, filed on Feb. 1, 2021, granted, now 11,398,933, issued on Jul. 26, 2022.
Application 17/164,325 is a continuation of application No. 16/741,099, filed on Jan. 13, 2020, granted, now 10,911,272, issued on Feb. 2, 2021.
Claims priority of provisional application 62/799,316, filed on Jan. 31, 2019.
Prior Publication US 2024/0223413 A1, Jul. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/03 (2006.01); H03K 5/135 (2006.01); H04L 25/02 (2006.01); H04L 27/01 (2006.01); H03K 5/00 (2006.01)
CPC H04L 25/03878 (2013.01) [H03K 5/135 (2013.01); H04L 25/028 (2013.01); H04L 25/03038 (2013.01); H04L 25/03057 (2013.01); H04L 27/01 (2013.01); H03K 2005/00052 (2013.01); H03K 2005/00065 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A decision feedforward equalizer (DFFE), comprising:
a plurality of precursor taps configured to sample an input signal by different time delay amounts;
a plurality of postcursor taps configured to sample the input signal by the different time delay amounts;
a plurality of tentative decision slicers configured to receive the delayed signals from the plurality of precursor taps and the plurality of postcursor taps, and to quantize the delayed signals to generate quantized sampled signals;
a plurality of multipliers configured to receive the quantized sampled signals as outputs of the plurality of tentative decision slicers; and
an adder configured to receive outputs of the plurality of multipliers.