	US 12,335,068 B2
	Multi-channel digital isolator with integrated configurable pulse width modulation interlock protection
Sadia Arefin Khan, Dallas, TX (US); Anant Shankar Kamath, Bengaluru (IN); Martin Staebler, Freising (DE); and Vikas Kumar Thawani, Bengaluru (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 1, 2023, as Appl. No. 18/241,544.
Application 18/241,544 is a continuation of application No. 17/352,663, filed on Jun. 21, 2021, granted, now 11,792,051.
Claims priority of provisional application 63/053,158, filed on Jul. 17, 2020.
Prior Publication US 2023/0412431 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/02 (2006.01); H02K 11/33 (2016.01); H02P 27/08 (2006.01); H03K 19/003 (2006.01); H03K 19/0175 (2006.01)

CPC H04L 25/0266 (2013.01) [H02K 11/33 (2016.01); H02P 27/08 (2013.01); H03K 19/00323 (2013.01); H03K 19/017509 (2013.01); H03K 19/017545 (2013.01)]

20 Claims

1. A method comprising:

transmitting a first input signal across an isolation barrier to generate a first received signal;

transmitting a second input signal across the isolation barrier to generate a second received signal;

providing the first received signal and a first signal to a first logic gate to generate a primary signal;

providing the second received signal and a second signal to a second logic gate to generate a secondary signal;

buffering the primary signal to generate a first output signal; and

buffering the secondary signal to generate a second output signal, and at any given time instant, only one of the first output signal and the second output signal is at logic high.