US 12,335,056 B2
Energy efficient ethernet (EEE) operation
Ragnar Hlynur Jonsson, Aliso Viejo, CA (US); Brian Edem, Saratoga, CA (US); Brett Anthony McClellan, Laguna Hills, CA (US); Seid Alireza Razavi Majomard, Belmont, CA (US); Xing Wu, Palo Alto, CA (US); and George Zimmerman, Manhattan Beach, CA (US)
Assigned to Marvell Asia Pte Ltd, Singapore (SG)
Filed by Marvell Asia Pte Ltd, Singapore (SG)
Filed on May 23, 2023, as Appl. No. 18/201,135.
Application 18/201,135 is a continuation in part of application No. 18/142,491, filed on May 2, 2023.
Claims priority of provisional application 63/344,730, filed on May 23, 2022.
Claims priority of provisional application 63/337,235, filed on May 2, 2022.
Claims priority of provisional application 63/337,240, filed on May 2, 2022.
Prior Publication US 2023/0353395 A1, Nov. 2, 2023
Int. Cl. G06F 1/26 (2006.01); H04L 7/00 (2006.01); H04L 12/12 (2006.01); G06F 1/3203 (2019.01)
CPC H04L 12/12 (2013.01) [H04L 7/0079 (2013.01); G06F 1/3203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A network interface device, comprising:
physical layer (PHY) circuitry comprising a transceiver, the PHY circuitry being configured to perform PHY functions associated with a communication link; and
a controller configured to:
operate the PHY circuitry in a normal receive operating mode in which the PHY circuitry continually receives transmission symbols from a link partner via the communication link,
determine that receive circuitry of the PHY circuitry is to transition to a low power mode in response to receiving a sleep signal from the link partner, and
in response to determining that the receive circuitry is to transition to the low power mode and after receiving the sleep signal, control the PHY circuitry to operate according to a quiet/refresh cycle of the low power mode to conserve power, the quiet/refresh cycle corresponding to a time schedule that includes i) alternating a) quiet time windows in which the PHY circuitry ignores transmissions from the link partner and b) alert time windows in which the PHY circuitry is prepared to receive a wake signal from the link partner, and ii) a refresh time window in which receive circuitry of the PHY circuitry is to be powered to receive a refresh signal from the link partner to facilitate keeping the receive circuitry of PHY circuitry synchronized with the link partner, including controlling the PHY circuitry to transition, immediately after transmission of the sleep signal, to a first-occurring quiet time window of the time schedule.