| CPC H04B 3/04 (2013.01) [H03K 5/01 (2013.01); H04L 12/40032 (2013.01); H03K 2005/00013 (2013.01); H04L 2012/40215 (2013.01); H04L 2012/40273 (2013.01)] | 8 Claims |

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1. A delay signal generation circuit, comprising:
first to nth delay circuits (n representing a natural number equal to or larger than 2); and
first to nth output terminals,
wherein,
the delay signal generation circuit is configured such that, in a first mode, an input signal passes through the first to kth (k representing a natural number equal to or larger than 1 but equal to or smaller than n) delay circuits in order and reaches the kth output terminal, and,
the delay signal generation circuit is configured such that, in a second mode, the input signal passes through the kth to nth delay circuits in reverse order and reaches the kth output terminal.
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