| CPC H03M 13/1111 (2013.01) [H03M 13/611 (2013.01)] | 20 Claims |
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1. A memory controller configured to control a memory module including a plurality of data chips, a first parity chip and a second parity chip, the memory controller comprising:
a system error correction code (ECC) engine; and
a processor configured to control the system ECC engine,
wherein the system ECC engine includes an ECC decoder and a memory configured to store a parity check matrix,
wherein the ECC decoder is configured to:
receive a read codeword set from the memory module;
select one of a plurality of ECC decoding schemes based on decoding status flags that are provided from the plurality of data chips and are different from the read codeword set, wherein each of the decoding status flags indicates whether at least one error bit is detected in a respective one of the plurality of data chips; and
correct a plurality of symbol errors in the read codeword set by performing an ECC decoding on the read codeword set based on the selected decoding scheme and the parity check matrix,
wherein the plurality of ECC decoding schemes include a first decoding and a second decoding, and
wherein, in response to the decoding status flags indicating that no error bits are detected in the plurality of data chips and a syndrome based on the read codeword set and the parity check matrix being non-zero, the ECC decoder is configured to perform the first decoding on the read codeword set.
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