US 12,334,942 B2
Phase locked loop having fast lock function
Young Jae Chang, Seoul (KR); Sung Ryong Lee, Seongnam-Si (KR); and Jae Sam Shim, Seoul (KR)
Assigned to SILICON MITUS, INC., Seongnam-Si (KR); and Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd, Hangzhou (CN)
Filed by SILICON MITUS, INC., Seongnam-Si (KR); and Hangzhou Silicon-Magic Semiconductor Technology Co., Ltd, Hangzhou (CN)
Filed on Jan. 29, 2024, as Appl. No. 18/425,818.
Claims priority of application No. 10-2023-0064415 (KR), filed on May 18, 2023.
Prior Publication US 2024/0388299 A1, Nov. 21, 2024
Int. Cl. H03L 7/10 (2006.01); H03L 7/085 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/104 (2013.01) [H03L 7/085 (2013.01); H03L 7/099 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A phase locked loop comprising:
a main voltage-controlled oscillator for which an oscillation frequency is adjusted by an offset current and a control voltage (Vctrl), the offset current being set by an offset current setting code (VCO_CON);
a phase frequency detector configured to adjust the control voltage by comparing an output signal (mCLK) of the main voltage-controlled oscillator and an input data signal (Data); and
an offset current setter configured to generate the offset current setting code for setting the offset current of the main voltage-controlled oscillator,
wherein the offset current setter comprises n sample voltage-controlled oscillators configured to generate n signals with different frequencies, respectively, and n counters configured to compare frequencies of each of the signals (sCLK) output from the n sample voltage-controlled oscillators and the input data signal, and is configured to generate the offset current setting code based on a comparison result of the n counters.