| CPC H03L 7/10 (2013.01) [H03K 3/037 (2013.01); H03L 7/093 (2013.01)] | 20 Claims |

|
1. An electronic device, comprising:
processing circuitry configured to generate a first input signal and a plurality of amplification parameters; and
a digital loop filter configured to generate a first output signal based at least on the first input signal and the plurality of amplification parameters, the digital loop filter comprising synchronization circuitry configured to align the first output signal with a clock signal via transmitting a first amplification parameter of the plurality of amplification parameters based on the clock signal and an enable signal.
|