US 12,334,938 B2
Digital frequency synthesizer
Gaurav Agrawal, Noida (IN); and Deependra Kumar Jain, Noida (IN)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Aug. 1, 2023, as Appl. No. 18/363,017.
Claims priority of application No. 202341038764 (IN), filed on Jun. 6, 2023.
Prior Publication US 2024/0413825 A1, Dec. 12, 2024
Int. Cl. H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/193 (2006.01)
CPC H03L 7/0818 (2013.01) [H03L 7/083 (2013.01); H03L 7/193 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a digital frequency synthesizer that comprises:
a first delay-locked loop (DLL) configured to receive a reference clock signal and generate a first plurality of delayed clock signals that are time-delayed versions of the reference clock signal;
a clock divider configured to execute an integer-division operation on a first delayed clock signal of the first plurality of delayed clock signals to generate an integer-divided clock signal;
control circuitry configured to generate, based on the integer-divided clock signal, fractional data that enables a fractional division associated with the digital frequency synthesizer;
a first clock selector configured to select, based on the fractional data, one of the first plurality of delayed clock signals as a first DLL clock signal;
a first output delay chain configured to generate a second plurality of delayed clock signals that are time-delayed versions of the first DLL clock signal;
a second clock selector configured to select, based on the fractional data, one of the second plurality of delayed clock signals as a first selected clock signal; and
a fractional clock generator configured to adjust the integer-divided clock signal based on the first selected clock signal and generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.