CPC H03L 7/0818 (2013.01) [H03L 7/083 (2013.01); H03L 7/193 (2013.01)] | 20 Claims |
1. An integrated circuit (IC), comprising:
a digital frequency synthesizer that comprises:
a first delay-locked loop (DLL) configured to receive a reference clock signal and generate a first plurality of delayed clock signals that are time-delayed versions of the reference clock signal;
a clock divider configured to execute an integer-division operation on a first delayed clock signal of the first plurality of delayed clock signals to generate an integer-divided clock signal;
control circuitry configured to generate, based on the integer-divided clock signal, fractional data that enables a fractional division associated with the digital frequency synthesizer;
a first clock selector configured to select, based on the fractional data, one of the first plurality of delayed clock signals as a first DLL clock signal;
a first output delay chain configured to generate a second plurality of delayed clock signals that are time-delayed versions of the first DLL clock signal;
a second clock selector configured to select, based on the fractional data, one of the second plurality of delayed clock signals as a first selected clock signal; and
a fractional clock generator configured to adjust the integer-divided clock signal based on the first selected clock signal and generate a fractional-divided clock signal that is a fractional-divided version of the reference clock signal.
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