| CPC H03K 5/14 (2013.01) [H03K 5/135 (2013.01)] | 8 Claims |
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1. A signal receiving circuit that receives first to third input signals, each having a different signal level at each unit interval (UI), the circuit comprising:
a first pulse generator for receiving a first differential signal obtained by subtracting the second input signal from the first input signal, and generating a first pulse that is high (H) at an edge of the first differential signal;
a second pulse generator for receiving a second differential signal obtained by subtracting the third input signal from the second input signal, and generating a second pulse that is high (H) at an edge of the second differential signal;
a third pulse generator for receiving a third differential signal obtained by subtracting the first input signal from the third input signal, and generating a third pulse that is high (H) at an edge of the third differential signal; and
a clock signal recovery unit for generating a recovery clock signal and a recovery clock delay signal, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including the first pulse, the second pulse, the third pulse, a first inversion pulse which is an inversion signal of the first pulse, a second inversion pulse which is an inversion signal of the second pulse, and a third inversion pulse, which is an inversion signal of the third pulse, wherein
the clock signal recovery unit includes:
a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and
a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node, wherein
a signal value of the input node and a signal value of the output node are in an inverse relationship.
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