US 12,334,934 B2
Delay adjustment circuit and distance measuring device
Mitsushi Tabata, Kanagawa (JP); Takashi Masuda, Kanagawa (JP); and Daisuke Suzuki, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 18/549,067
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Mar. 2, 2022, PCT No. PCT/JP2022/008896
§ 371(c)(1), (2) Date Sep. 5, 2023,
PCT Pub. No. WO2022/190997, PCT Pub. Date Sep. 15, 2022.
Claims priority of application No. 2021-040385 (JP), filed on Mar. 12, 2021.
Prior Publication US 2024/0072781 A1, Feb. 29, 2024
Int. Cl. H03K 5/133 (2014.01); G01S 7/4915 (2020.01); H03K 5/156 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/133 (2013.01) [G01S 7/4915 (2013.01); H03K 5/1565 (2013.01); H03K 2005/00071 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A delay adjustment circuit, comprising:
a plurality of delay adjustment units connected in series, wherein each of the delay adjustment units including:
one or more first delay elements, connected in series, configured to delay an input signal based on a clock, and
a first selector configured to output one of the input signal or an output of a first delay element at a last stage among the one or more first delay elements; and
an output unit configured to output the clock based on an output of the first selector included in a delay adjustment unit of a last stage among the plurality of delay adjustment units, wherein each of the plurality of delay adjustment units includes a different number of the first delay elements.