| CPC H03K 5/133 (2013.01) [H03K 5/00006 (2013.01); H03K 5/135 (2013.01); H03K 2005/00065 (2013.01)] | 20 Claims |
|
1. A power management integrated circuit, comprising:
a clock generator that generates an input clock;
a first phase delay controller that delays the input clock by a first phase and outputs a first supply clock to a first switching converter;
a second phase delay controller that delays the input clock by a second phase and outputs a second supply clock to a second switching converter; and
a third phase delay controller that delays the input clock by a third phase and outputs a third supply clock to a third switching converter,
wherein the input clock input to the first phase delay controller, the second phase delay controller, and the third phase delay controller has the same phase,
wherein the first phase, the second phase and the third phase have different phases from each other,
wherein the first to third phase delay controllers output the first to third supply clocks based on different first, second and third selection signals from each other, wherein the first, second and third selection signals are separately provided.
|