US 12,334,932 B2
Eye expander for PAM4 signal linearization
Shita Guo, Dallas, TX (US); and Amit S. Rane, Santa Clara, CA (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 28, 2022, as Appl. No. 17/587,095.
Prior Publication US 2023/0246636 A1, Aug. 3, 2023
Int. Cl. H03K 5/12 (2006.01); H03K 5/02 (2006.01); H03K 5/1252 (2006.01); H03K 17/56 (2006.01)
CPC H03K 5/1252 (2013.01) [H03K 5/02 (2013.01); H03K 17/56 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An eye expander comprising:
a first input terminal;
a second input terminal;
a first output terminal;
a second output terminal;
a first gain stage further including:
a first transistor coupled to the first output terminal and to the first input terminal; and
a second transistor coupled to the second output terminal and to the second input terminal;
one or more primary resistor-transistor pairs coupled to the first transistor and the second transistor, each primary resistor-transistor pair configured to be coupled to a bias voltage terminal; and
a second gain stage further including:
a third transistor coupled to the second output terminal and to the first input terminal;
a fourth transistor coupled to the first output terminal and to the second input terminal, and a current terminal of the fourth transistor is coupled to a current terminal of the third transistor at a first node;
a first switch having a first terminal coupled to the first node and having a control terminal configured to be coupled to one of the bias voltage terminal and a ground terminal; and
a plurality of first resistor-transistor pairs coupled in parallel between a second terminal of the first switch and the ground terminal, each operable to selectively couple the first node to the ground terminal responsive to a first control signal and a second control signal; and
a third gain stage further including:
a fifth transistor coupled to the first output terminal and to the first input terminal;
a sixth transistor coupled to the second output terminal and to the second input terminal;
a first resistor coupled between a current terminal of the fifth transistor and a second node;
a second resistor coupled between a current terminal of the sixth transistor and the second node;
a second switch having a first terminal coupled to the second node and having a control terminal configured to be coupled to one of the bias voltage terminal and the ground terminal; and
a plurality of second resistor-transistor pairs coupled in parallel between a second terminal of the second switch and the ground terminal, each operable to selectively couple the second node to the ground terminal responsive to the first control signal and the second control signal.