US 12,334,930 B2
Low latency phase alignment for parallel data paths
Riyas Noorudeen Remla, Singapore (SG); and Showi-Min Shen, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Mar. 30, 2023, as Appl. No. 18/128,945.
Prior Publication US 2024/0333270 A1, Oct. 3, 2024
Int. Cl. H03K 5/01 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/01 (2013.01) [H03K 2005/00078 (2013.01); H03K 2005/00286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A receiver circuitry comprising:
first data path circuitry configured to receive a first data signal based on a capture clock signal, the first data signal output based on a first launch clock signal;
second data path circuitry configured to receive a second data signal based on the capture clock signal, the second data signal output based on a second launch clock signal; and
phase alignment circuitry configured to:
adjust a phase of the first launch clock signal and a phase of the second launch clock signal based on a first clock slip signal and a second clock slip signal, respectively; and
adjust a phase of the capture clock signal relative to one of the first launch clock signal and the second launch clock signal based on a first adjustment value associated with the first data path circuitry and a second adjustment value associated with the second data path circuitry.