US 12,334,924 B2
Methods and apparatus to prevent lock-up of high-speed pseudo-differential frequency divider circuits
Robert Taft, Munich (DE); Alexander Bodem, Freising (DE); Filip Savic, Munich (DE); Paul Kramer, Timnath, CO (US); and Vineethraj Rajappan Nair, Freising (DE)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Aug. 30, 2023, as Appl. No. 18/240,278.
Prior Publication US 2025/0080117 A1, Mar. 6, 2025
Int. Cl. G06F 1/08 (2006.01); H03K 19/20 (2006.01); H03K 21/00 (2006.01)
CPC H03K 21/00 (2013.01) [G06F 1/08 (2013.01); H03K 19/20 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first gated inverter having an input and an output;
a second gated inverter having an input and an output;
a third gated inverter having an input and an output;
a fourth gated inverter having an input and an output;
a first inverter having an input and an output, the output of the first inverter coupled to the input of the second gated inverter;
a second inverter having an input and an output, the output of the second inverter coupled to the input of the third gated inverter;
a fifth gated inverter having an output coupled to the input of the first gated inverter and the input of the first inverter;
a sixth gated inverter having an output coupled to the input of the second inverter and the input of the fourth gated inverter;
a seventh gated inverter having an input coupled to the output of the first gated inverter and the output of the third gated inverter; and
an eighth gated inverter having an input coupled to the output of the second gated inverter and the output of the fourth gated inverter.