US 12,334,923 B1
Multi-cycle reset mechanism for a chain of majority gates having non-linear polar material
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Oct. 1, 2021, as Appl. No. 17/449,784.
Application 17/449,784 is a continuation of application No. 17/449,748, filed on Oct. 1, 2021.
Int. Cl. H03K 19/23 (2006.01); G11C 11/22 (2006.01); H10B 53/40 (2023.01); H10D 1/68 (2025.01)
CPC H03K 19/23 (2013.01) [G11C 11/221 (2013.01); H10B 53/40 (2023.02); H10D 1/682 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first logic comprising a 5-input majority gate including a first input, a second input connected to the first input, a third input, a fourth input coupled to a carry input, and a fifth input coupled to a sum input, wherein an output of the first logic is a sum output;
a second logic coupled to the first logic, wherein the second logic includes a 3-input majority or minority gate, wherein the 3-input majority or minority gate includes a sixth input, a seventh input coupled to the carry input, and an eighth input coupled to the sum input; and
a reset mechanism to reset the first logic and the second logic in at least two cycles, wherein the reset mechanism is to condition the first input, the second input, the third input, the fourth input, the fifth input, the sixth input, the seventh input, and the eighth input in a reset phase separate from an evaluation phase.