| CPC H03K 19/0823 (2013.01) | 15 Claims |

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1. A ternary logic element comprising:
a transistor including a channel layer containing silicon, an input electrode, an output electrode, and a control electrode; and
a switching element which includes an emitter, a base extending from the emitter, and a collector extending from the base and in which any one of the emitter and the collector is electrically connected to the channel layer and is connected to the transistor in series,
wherein each of the emitter, the base, and the collector includes silicon,
each of the emitter and the collector is doped with any one of an n-type dopant and a p-type dopant, and the base is doped with the other type of dopant,
a first portion and a second portion spaced apart from the first portion of the channel layer are each doped with the one type of dopant, a third portion disposed between the first portion and the second portion is doped with the other type of dopant, and the first portion and the second portion are in contact with the input electrode and the output electrode, respectively,
when a first control voltage is applied to the control electrode, a first voltage is output,
when a second control voltage different from the first control voltage is applied to the control electrode, a second voltage different from the first voltage is output, and
when a third control voltage different from the first control voltage and the second control voltage is applied to the control electrode, a third voltage different from the first voltage and the second voltage is output.
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