US 12,334,921 B2
High speed dual-tail latch with power gating
Jinha Hwang, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 13, 2023, as Appl. No. 18/507,314.
Claims priority of provisional application 63/448,858, filed on Feb. 28, 2023.
Prior Publication US 2024/0291492 A1, Aug. 29, 2024
Int. Cl. H03K 19/0185 (2006.01); H03F 3/45 (2006.01); H03K 3/012 (2006.01); H03K 3/356 (2006.01)
CPC H03K 19/018528 (2013.01) [H03F 3/45183 (2013.01); H03K 3/012 (2013.01); H03K 3/35613 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first sensing stage configured to sense a voltage differential of a data signal (DQ) and a reference signal (VRDQ) and output a first amplified voltage differential, wherein the first amplified voltage differential comprises a first voltage at a first output node and a second voltage at a second output node; and
a second sensing stage configured to sense the first amplified voltage differential and output a second amplified voltage differential, where the second amplified voltage differential comprises a third voltage at a third output node and a fourth voltage at a fourth output node;
wherein a first power gating circuit is coupled to the third output node and a second power gating circuit is coupled to the fourth output node;
wherein the first power gating circuit comprises a first p-channel transistor coupled to the third output node to increase transconductance at the third output node, and wherein the second power gating circuit comprises a second p-channel transistor coupled to the fourth output node to increase transconductance at the fourth output node;
wherein the second sensing stage comprises a first n-channel transistor coupled in series with the first p-channel transistor and to the third output node;
wherein the second sensing stage comprises a second n-channel transistor coupled in series with the second p-channel transistor and to the fourth output node;
wherein the gate of each of the of the first n-channel transistor and the first p-channel transistor receives the first voltage from the first output node; and
wherein the gate of each of the of the second n-channel transistor and the second p-channel transistor receives the second voltage from the second output node.