US 12,334,919 B2
Combined function IC cell layout method and system
Ying Huang, Hsinchu (TW); Changlin Huang, Hsinchu (TW); Jing Ding, Hsinchu (TW); and Qingchao Meng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Naning (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC NANJING COMPANY, LIMITED, Nanjing (CN)
Filed on Oct. 6, 2023, as Appl. No. 18/482,172.
Application 18/482,172 is a continuation of application No. 17/830,601, filed on Jun. 2, 2022, granted, now 11,784,646.
Claims priority of application No. 202210585532.0 (CN), filed on May 27, 2022.
Prior Publication US 2024/0030921 A1, Jan. 25, 2024
Int. Cl. H03K 19/0185 (2006.01); G06F 30/392 (2020.01); G06F 119/06 (2020.01)
CPC H03K 19/018521 (2013.01) [G06F 30/392 (2020.01); G06F 2119/06 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
arranging a first portion of first through fourth pluralities of active regions and a first portion of a plurality of gate regions of a cell as a functional circuit in a first portion of the cell;
arranging a second portion of the first through fourth pluralities of active regions and a second portion of the plurality of gate regions of the cell as one of a decoupling capacitor or an antenna diode in a second portion of the cell,
wherein the one of the decoupling capacitor or the antenna diode comprises at least one active region of the second portion of the first through fourth pluralities of active regions; and
storing an IC layout diagram of the cell in a storage device.