US 12,334,918 B1
Stacked non-planar capacitors based multi-function linear threshold gate with input based adaptive threshold
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Rajeev Kumar Dokania, Beaverton, OR (US); Debo Olaosebikan, San Francisco, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/552,048.
Application 17/552,048 is a continuation of application No. 17/550,919, filed on Dec. 14, 2021.
Int. Cl. H03K 19/00 (2006.01); H01L 49/02 (2006.01)
CPC H03K 19/0027 (2013.01) [H01L 28/56 (2013.01); H01L 28/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, wherein the via couples to a first metal layer;
a first capacitor including a linear dielectric material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;
a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;
a first input line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first input line is on an outer portion of the first capacitor;
a second input line extending along the x-plane or the z-plane, wherein the second input line is on an output portion of the second capacitor; and
a first transistor coupled to the via and a supply rail.