US 12,334,877 B2
Power amplifier circuit, transmitter, and network device
Jie Sun, Shanghai (CN); Yijun Sun, Chengdu (CN); Hailei Suo, Chengdu (CN); Jinhu Chen, Chengdu (CN); and Song Li, Kista (SE)
Assigned to HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed by HUAWEI TECHNOLOGIES CO., LTD., Shenzhen (CN)
Filed on Mar. 15, 2022, as Appl. No. 17/695,065.
Application 17/695,065 is a continuation of application No. PCT/CN2019/105943, filed on Sep. 16, 2019.
Prior Publication US 2022/0200541 A1, Jun. 23, 2022
Int. Cl. H03F 1/42 (2006.01); H03F 1/56 (2006.01); H03F 3/24 (2006.01)
CPC H03F 1/42 (2013.01) [H03F 1/56 (2013.01); H03F 3/245 (2013.01); H03F 2200/222 (2013.01); H03F 2200/387 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power amplifier circuit, wherein the power amplifier circuit comprises:
N input ports, N power amplifier branches, one combiner circuit, and one output port, wherein
each of the N input ports is connected to a corresponding power amplifier branch in the N power amplifier branches, each of the N power amplifier branches is connected to the combiner circuit, and the combiner circuit is further connected to the output port;
each of the N input ports is configured to input a corresponding input signal;
the N power amplifier branches and the combiner circuit are configured to perform power amplification and combining on N input signals, to generate an output signal; and
the output port is configured to output the output signal, wherein
the N power amplifier branches comprise one first power amplifier branch and N−1 second power amplifier branches, the first power amplifier branch operates in a class AB or class B operating mode, the N−1 second power amplifier branches operate in a class C operating mode with different gate bias voltages, the gate bias voltages of the N−1 second power amplifier branches become lower in order, and N is a positive integer greater than 2;
wherein the combiner circuit comprises N−1 couplers and N−1 impedance matching circuits;
a first impedance matching circuit of the N−1 impedance matching circuits is between two adjacent couplers of the N−1 couplers, and a second impedance matching circuit of the N−1 impedance matching circuits is between the output port and a coupler of the N−1 couplers; and
an isolated port of a first coupler of the N−1 couplers is connected to an output of the first power amplifier branch, and two balance ports of each of the N−1 couplers each are connected to a corresponding one of the N−1 second power amplifier branches.