US 12,334,875 B2
Semiconductor device and operation method thereof
Kei Takahashi, Isehara (JP); and Takayuki Ikeda, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/632,284
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Aug. 20, 2020, PCT No. PCT/IB2020/057814
§ 371(c)(1), (2) Date Feb. 2, 2022,
PCT Pub. No. WO2021/038390, PCT Pub. Date Mar. 4, 2021.
Claims priority of application No. 2019-156546 (JP), filed on Aug. 29, 2019.
Prior Publication US 2022/0302880 A1, Sep. 22, 2022
Int. Cl. H03F 1/26 (2006.01); H03F 3/00 (2006.01); H03F 3/387 (2006.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)
CPC H03F 1/26 (2013.01) [H03F 3/005 (2013.01); H03F 3/387 (2013.01); H03F 2200/372 (2013.01); H10B 12/00 (2023.02); H10D 30/6734 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10D 87/00 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a switch;
first and second capacitors;
first and second chopping circuits;
an amplifier;
first and second input terminals; and
first and second output terminals,
wherein the amplifier comprises a non-inverting input terminal, an inverting input terminal, an inverting output terminal, and a non-inverting output terminal,
wherein the semiconductor device electrically connects the first input terminal and one terminal of the first capacitor, electrically connects the second input terminal and one terminal of the second capacitor, directly connects the other terminal of the first capacitor and the first output terminal, and directly connects the other terminal of the second capacitor and the second output terminal in a first period,
wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal in the first period,
wherein the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal in the first period,
wherein the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal in a second period,
wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the non-inverting input terminal and electrically connects the other terminal of the second capacitor and the inverting input terminal in the second period,
wherein the second chopping circuit electrically connects the inverting output terminal and the first output terminal and electrically connects the non-inverting output terminal and the second output terminal in the second period,
wherein the semiconductor device electrically connects the one terminal of the first capacitor and the first output terminal and electrically connects the one terminal of the second capacitor and the second output terminal in a third period,
wherein the first chopping circuit electrically connects the other terminal of the first capacitor and the inverting input terminal and electrically connects the other terminal of the second capacitor and the non-inverting input terminal in the third period, and
wherein the second chopping circuit electrically connects the non-inverting output terminal and the first output terminal and electrically connects the inverting output terminal and the second output terminal in the third period.