US 12,334,874 B2
High frequency amplifier
Tatsuya Hashinaga, Osaka (JP); and Yutaka Moriyama, Osaka (JP)
Assigned to SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
Appl. No. 17/757,310
Filed by SUMITOMO ELECTRIC INDUSTRIES, LTD., Osaka (JP)
PCT Filed Jan. 5, 2021, PCT No. PCT/JP2021/000127
§ 371(c)(1), (2) Date Jun. 14, 2022,
PCT Pub. No. WO2021/141030, PCT Pub. Date Jul. 15, 2021.
Claims priority of application No. 2020-002882 (JP), filed on Jan. 10, 2020.
Prior Publication US 2022/0376658 A1, Nov. 24, 2022
Int. Cl. H03F 3/68 (2006.01); H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03F 3/60 (2006.01)
CPC H03F 1/0288 (2013.01) [H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/602 (2013.01); H03F 2200/451 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A high frequency amplifier comprising:
an asymmetric Doherty amplifier configured to amplify a high frequency signal having a wavelength λ, the high frequency signal being input, and the asymmetric Doherty amplifier including a carrier amplifier and a peak amplifier, the peak amplifier being configured to start an amplifying operation when an output of the carrier amplifier reaches a saturation region and having a saturation output different from a saturation output of the carrier amplifier;
a driver amplifier configured to drive the asymmetric Doherty amplifier;
a branch circuit configured to branch the high frequency signal amplified by the driver amplifier into an input path on a peak amplifier side and an input path on a carrier amplifier side;
a phase adjustment circuit configured to delay either a phase of a signal input to the peak amplifier or a phase of a signal input to the carrier amplifier, the phase adjustment circuit being provided on either the input path on the peak amplifier side or the input path on the carrier amplifier;
a first substrate on which the carrier amplifier and the peak amplifier are mounted; and
a second substrate on which the driver amplifier, the branch circuit, and the phase adjustment circuit are mounted,
wherein an input terminal of the driver amplifier and an input terminal of the carrier amplifier are disposed at positions where the input terminal of the driver amplifier and the input terminal of the carrier amplifier project to each other when the second substrate is stacked on the first substrate, and
wherein an electrical length from the input terminal of the driver amplifier to an output terminal of the carrier amplifier is set to a phase of (2n+1)×π, where n is an integer greater than or equal to 0.