US 12,334,872 B2
Data driving circuit and display including the same
Yong Sung Ahn, Daejeon (KR); Ji Won Kim, Daejeon (KR); Hyo Joong Kim, Daejeon (KR); Kyung Min Shin, Daejeon (KR); Kyu Tae Lee, Daejeon (KR); and Ha Rim Choi, Daejeon (KR)
Assigned to LX SEMICON CO., LTD., Daejeon (KR)
Filed by LX SEMICON CO., LTD., Daejeon (KR)
Filed on Oct. 13, 2023, as Appl. No. 18/486,715.
Claims priority of application No. 10-2022-0131483 (KR), filed on Oct. 13, 2022.
Prior Publication US 2024/0128930 A1, Apr. 18, 2024
Int. Cl. H03F 1/02 (2006.01); G09G 3/20 (2006.01); G09G 3/3233 (2016.01); G09G 3/3275 (2016.01); H03F 3/45 (2006.01); H03F 3/68 (2006.01)
CPC H03F 1/02 (2013.01) [G09G 3/2007 (2013.01); G09G 3/3233 (2013.01); G09G 3/3275 (2013.01); H03F 3/45076 (2013.01); H03F 3/68 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0291 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0673 (2013.01); H03F 2203/45044 (2013.01); H03F 2203/45214 (2013.01); H03F 2203/45296 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A gamma voltage generation circuit comprising:
a first multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through a first resistor string;
a second multiplexer configured to select and supply with a voltage between a maximum reference voltage and a minimum reference voltage through the first resistor string;
a second resistor string;
a first operational amplifier circuit connected to an uppermost end of the second resistor string and configured to output a first voltage corresponding to a highest voltage of the second resistor string based on the voltage received from the first multiplexer;
a second operational amplifier circuit connected to a lowest end of the second resistor string and configured to output a second voltage corresponding to a lowest voltage of the second resistor string based on the voltage received from the second multiplexer; and
a third operational amplifier circuit connected to a node of the second resistor string and configured to divide the first voltage and the second voltage and to output a third voltage,
wherein the third operational amplifier circuit includes a first offset elimination circuit that is configured to eliminate an offset voltage through charging and discharging of a capacitor, and
the first operational amplifier circuit and the second operational amplifier circuit are configured to eliminate an offset voltage in a manner different from that of the third operational amplifier circuit by a chopping method.