US 12,334,826 B2
Peak current limit management for high frequency buck converter
Janne Matias Pahkala, Oulu (FI); Jussi Matti Aleksi Särkkä, Oulunsalo (FI); and Juha Olavi Hauru, Oulu (FI)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 15, 2024, as Appl. No. 18/442,596.
Application 18/442,596 is a continuation of application No. 17/564,334, filed on Dec. 29, 2021, granted, now 11,949,333.
Prior Publication US 2024/0195300 A1, Jun. 13, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 1/32 (2007.01)
CPC H02M 3/158 (2013.01) [H02M 1/0054 (2021.05); H02M 1/32 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A controller circuit, comprising:
a current comparison circuit having at least four comparators configured to:
compare a voltage of an output circuit to respective reference voltages; and
compare a sensed current from the output circuit to a first set of current limits defining an upper current limit range, and to a second set of current limits defining a lower current limit range; and
a switching regulator control circuit configured to receive outputs from the comparators, and generate a control signal for alternatingly switching first and second transistors off and on, such that the first transistor is off when the second transistor is on, and the second transistor is off when the first transistor is on.